Signal locking systems typically rely on phase detectors in order to approximate the adjustment or gain factor to be applied to an output clock so as to coincide in time with an input reference signal clock. Typically, a phase difference between two clock sources of zero degrees is the design target in a standard phase-locked loop (PLL) system. PLL circuits can be implemented in either predominately digital or analog fashion, where the primary difference is in the way the output clock function is constructed. The analog PLL may, for example, employ a voltage-controlled oscillator (VCO), while a digital PLL may employ a digital accumulator circuit where the most significant bit (MSB) is typically used to form the output clock. In typical digital PLL circuits, the phase difference measurements are often limited by the frequency of the digital system clock. For example, where the digital system clock is running at a frequency of 200 MHz, the phase difference measurement resolution is only 5 ns, or the period of the system clock. Thus, the minimum PLL system output jitter and wander, which are essentially system error factors, would also be 5 ns in this example case.
FIG. 1 shows a type of phase detector, indicated by the general reference character 100, that is capable of very good phase resolution. INPUT 1 signal 104 connects to the D-input of D-type flip-flop (DFF) 102. INPUT 2 signal 106 connects to the clk-input of the DFF and the output 108 connects to the Q-output of the DFF. One of INPUT 1 or INPUT 2 may represent a feedback clock and the other a reference clock in a PLL system, for example. This circuit indicates the order of the signals based on the first transition edge (i.e., low-to-high or rising transition). The output 108 goes low if the INPUT 1 rising edge occurs after the INPUT 2 rising edge, but the output goes high if the INPUT 1 rising edge occurs prior to the INPUT 2 rising edge. This phase detection approach has the advantage of infinitesimally small timing resolution, but the disadvantage is that the gain, or the ratio of the increase in oscillator output frequency to the input phase difference, is very high and, as such, is very difficult to control.
The PLL system application requires a defined measurement of the input phase difference in order for the system to subsequently have a defined gain, bandwidth, and damping factor. The bandwidth is essentially the frequency range over which the PLL system allows stable operation. The damping factor indicates how well a system is damped and, as it follows, how much ringing is produced after an input signal disturbance. Common digital phase measurement techniques, such as those employing the standard type 4 phase and frequency detector circuit are able to indicate the relative phase difference of two signals, but this approach is limited by the system clock and its general digital nature. As such, the resolution is insufficient to avoid excessive output jitter and wander in the phase-locked position, as described above. For the phase detector shown in FIG. 1, superior timing resolution is achieved, but the gain of this detector is not controllable and, thus, the associated PLL system dynamics of bandwidth and damping factor would also be uncontrollable.
As described, common phase detection approaches, particularly those used in digital-based signal locking systems like digital PLLs, typically suffer from either insufficient phase difference resolution for the application or uncontrollable gain.
It would be desirable to arrive at some way of providing phase difference information and control that would enable very high input phase difference resolution along with controllable PLL dynamics in an implementation that would remain reliable over the expected operating conditions and process variations.